Formal-verification tools for embedded software development

Users of generic software-development tools from now on have an opportunity to use formal methods to aid with code verification. The products introduced is a high-level tool for project specification and validation; while another one is a software-design-support instrument which spans the requirements analysis via test, supplied with automated generation of code and iterative refinement of code. Integration with the new software product covers model checking and automated generation of tests for embedded software projects. Checking of models verifies that design structure corresponds to specification of requirements; i.e. It does everything it is supposed to do and nothing more or less. Such verification ensures that your software will not conduct unexpectedly and all actions will be completely envisaged.

Due to automated test generation, one can create test cases from the design models and enhance code quality by covering a more extended range of test scenarios. Industry professionals say that test is the weak point in generic embedded code development due to human inability to predict and test all unexpected cases; formal methods enable you to completely explore all available paths through the software. Formal methods were utilized in hardware development, mainly in equivalence checking to make sure that a set of data functions the same way before and after a transformation. These methods were hardly applicable to software with respect to great amount of degrees of freedom allowed by software. To handle a software, you need to be able to promptly point out, classify and dismiss problematic sectors.